If theres a very important factor thats cheaper than creating a new fab, its expanding a preexisting one. Intels Oregon D1 facility has been the hub of most of its technology advancements in the last 20 years, whereby Intel will trial new manufacturing processes before transferring them to other fabs all over the world. Obviously, the website in Hillsboro is really a big facility, sprawling over some 530 acres and hiring 14000 employees, making Intel the largest employer in Portland. As once was announced, Intel will be expanding its fab at Hillsboro to support more tools, more capacity, and much more research. Today, that expansion is officially being opened: enter D1X Mod 3.
The brand new Mod 3 extension of the D1X fab can be an impressive, with Intel stating that it has generated 270,000 square foot more clean room space, or the same as 3.5 football fields (for context, the brand new site announced at Magdeburg is 2 football fields, or 165k square feet). I visited the facility back December, where it seemed the construction of the shell was complete, the clean room area had been integrated into the others of D1X, however they were along the way of installing tools. Intel stated to us that technically D1X Mod 3 might have been opened at a number of times, although they chose this date because (a) were moving to warmer weather for the function, and (b) its a period they could obtain the municipality dignitaries to wait, like a state governor.
Intels full facility, like the fabs and the study areas, is on a niche site called Ronler Acres. Within the announcement today, Ronler Acres is usually to be renamed after among the companies co-founders, and the brand new name may be the Gordon Moore Park. The entire cost of the expansion and renaming is north of $3B+, although this doesnt include all of the extra equipment for the cleanroom. The facility isnt filled with hardware section of that extra 270k square foot is for future expansion as more tools are essential and much more are delivered. With current lead times for semiconductor tooling supposedly going beyond 18 months, that is perhaps to be likely. Intel states that the Gordon Moore Park site will host the initial High-NA machines from ASML, and become the website of ramping the technology for customer high-volume manufacturing in 2025.
On that time, section of todays announcement is really a continuation of what we heard from Dr. Ann Kelleher, Intels VP of Technology Development Intel is enabling a dual track effort for future process node technologies in a way that regular EUV may be used completely down from Intel 4 to Intel 3 to Intel 20A to Intel 18A (and beyond), while High-NA EUV will intercept that roadmap when it’s ready, and technologies can be constructed with either when High-NA takes longer to implement.
Intel also shed some light on an interior test node they are focusing on. The mantra from the CEO Pat Gelsinger has gone to deliver 5 process node technologies in 4 years, however internally there’s another node thats being given equal treatment. Intel has recently announced PowerVia, its technology for backside power delivery because of intercept the timeline with Intel 20A alongside RibbonFET, however in order to obtain a handle on the brand new manufacturing techniques required, Intel includes a Risk Reduction Test Node to access grips with it before mainstream production.
This test node uses exactly the same Intel 4/Intel 3 FinFET designs because of its transistors, but separates the energy lines and signal layers to separate sides of the transistor. In Intel 20A, the transistors in the center of this sandwich will undoubtedly be RibbonFETs, however the test node for PowerVias is required to ensure that yields can scale. Intel stated that test node, sort of Intel 3b, will still obtain the same attention for risk management and yield scaling as any regular production node. We have to declare that Intel has mentioned this risk node before, but we were beneath the impression it had been being done on a 14nm or 10nm process that was already high-yielding, as opposed to the industry leading that still must reach that level.
Intel was asked if this Intel 3b test node, using FinFET + PowerVia, would ever reach productization the solution was that although its obtaining the same treatment as a production node, you can find currently no plans to go it to full production, and you can find no customer chips being made with it. This last element is essential, as we understand that customers already are dealing with Intel 3 and Intel 20Something design flows ready for when Intel could make those manufacturing processes available.
The final final note of the announcement is some timeline adjustment with Intels future node technologies. Up to now, Intel has stated that the Intel 18A node arrives for 2025, but this date is currently changing to late 2024, attracting the date by at the very least 25 %. Intel confirmed that’s because a few of the key metrics they use to find out once the technology will undoubtedly be ready already are meeting targets before schedule, therefore enough confidence was there to create this change. This means that in 2024, we ought to expect 20A in the initial half, and 18A in the next half. That said, some in the semiconductor space are wondering if 20A is somewhat of a pipecleaner, and 18A is intended to function as long-life node, comparable to where 14nm is today on Intels roadmap.
Compiled by Dr. Ian Cutress, Chief Analyst of A LOT MORE THAN Moore
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